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w523sxx (preliminary) high fidelity p ower s peech tm publication release date:oct. 2000 - 1 - revision a5 general description the w523sxx family are programmable speech synthesis ics that utilize winbond s new high fidelity voice synthesis algorithm to generate all types of voice effects with high sound quality. the w523sxx ? s load, jump, move and inc commands and ten programmable registers provide powerful user - programmable functions that make this chip suitable for an extremely wide range of speech ic applications. the w523sxx family includes 14 kinds of bodies which are the same except for the voice duration shown below: part no. w523s08 w523s10 w523s12 w523s15 w523s20 w523s25 w523s30 duration 8 sec. 10 sec. 12 sec. 15 sec. 20 sec. 25 sec. 30 sec. part no. w523s40 W523S50 w523s60 w523s70 w523s80 w523s99 w523m02 duration 40 sec. 50 sec. 60 sec. 70 sec. 80 s ec. 100 sec. 120 sec. note: the voice duration is estimated by 6.4 khz sampling rate. features operating voltage range: 2.4 ? 5.5 volts for both dac and pwm output new high fidelity synthesis algorithm either pwm mode or d/a converter mode can be selecte d for aud output provides 4 direct trigger inputs that can easily be extended to 24 matrix trigger inputs two trigger input debounce times (50 ms or 400 us) can be set provides up to 2 leds and 5 stop outputs flexible functions programmable through the fol lowing: - ld (load), jp (jump), mv (move) and inc (increase) commands - four general purpose registers: r0, r1, r2 and r3 - six special purpose registers: en0, en1, mode0, mode1, stop and page - conditional instructions: @last, @tgn_high or low, where, n = 1,2 ,5 or 6 - speech equations - end instruction supports cpu interface operation symbolic compiler supported instruction cycle 400 m s typically section control for - variable frequency: 4.8/6/8/12 khz
w523sxx (preliminary) - 2 - - led: on/off up to 256 voice groups can be used in sin gle page mode; or extended to 2,048 voice groups in multi page mode, such as 8 - page, 16 - page and 32 - page. block diagram osc vdd1 reset test tg1 tg2 tg5 tg6 vss1 led1 pin description controller rom speech synthesizer pwm driver d/a converter timing generator stpa/busy stpb led2/stpc stpd stpe vss2 vdd2 spk+/aud spk -
w523sxx (preliminary) publication release date: oct 2000 - 3 - revision a5 name i/o description osc i ring oscillator input v dd1 - positive power supply test i test pin. internally pulled low reset i active low to reset all devices as por function. internally pulled high. tg1 i direct trigger input 1. internally pulled high tg2 i direct trigger input 2. internally pulled high tg5 i direct trigger input 5. internally pulled high t g6 i direct trigger input 6. internally pulled high v ss1 - negative power supply led1 o led1 output stpa/busy o stop signal a or busy signal stpb o stop signal b led2/stpc o led2 output or stop signal c stpd o stop signal d stpe o stop signal e spk - o pwm output aud/spk+ o current type output or pwm output for speaker vss2 - negative power supply vdd2 - positive power supply functional descripti on i/o pins : the w523sxx family provides up to 4 trigger pins, which can be extended to 24 matrix tr igger inputs, up to 5 stop output pins and up to 2 led output pins. all of these i/o pins ? status can be easily defined by powerspeech ? program. powerful programmable features : the w523sxx family provides jump (jp), load (ld), move (mv), inc, and end comm ands and 10 programmable registers, such as r0 ~ r3, en0, en1, mode0, mode1, stop and page, can be easily used to program the desired playing mode, stop output signal form, led flash type, and trigger pin interrupt modes. the chip ? s programmable features c an also be used to develop new, customized functions for a wide variety of innovative applications. programmable power - on initialization : whenever the w523sxx is powered on or pressed the reset pin, the program contained in the 32 nd voice group will be executed after the power - on delay (about 160 ms), so the user can write a program into this group to set the power - on initial state. if user does not wish to execute a program at
w523sxx (preliminary) - 4 - power - on, an ? end ? instruction should be entered in the group 3 2. the interruption priority is shown as below while other trigger pins as well as jump (jp) command are executing simultaneously during poi executing period: poi > tg1f > tg1r > tg2f > tg2r > tg5f > tg5r > tg6f > tg6r > "jp" instruction. register definit ion and control the register file in the w523sxx family is composed of 10 registers, including 4 general - purpose registers and 6 special purpose registers. they are defined to facilitate the operations for various purposes. the default setting values of th e registers are given in the following table. register name default setting general register r0 - r3 00100000b en0 xx11xx11b en1 xx11xx11b mode0, mode1 11111111b stop xxx11111b special register page 00000000b 1. mode0 register bit description de finition 1: flash 7 led mode 0: dc 1: led2 output 6 led2/stpc pin selection 0: stpc output 1: long 4 debounce time 0: short 1: stpa output 2 stpa/busy pin selection 0: busy output 5,3,1,0 x don ? t care the mode0.7 bit defines the output ty pe of led1 and led2 pins as flash output (3 hz) or dc output. the mode0.6 bit defines the configuration of led2/stpc pin ? s status as led2 output or stpc output. the mode0.4 bit defines the trigger pin ? s debounce time as long debounce (50 ms) or short debou nce (400 us). the mode0.2 bit defines the behavior of the stpa/busy pin as stpa output in normal mode or busy signal output in cpu mode. the bits 5, 3, 1 and 0 are don ? t care bits.
w523sxx (preliminary) publication release date: oct 2000 - 5 - revision a5 2. mode1 register bit description definition 7, 6, 1, 0 x don ? t care 1: alternate 5 led flash type 0: synchronous 1: yes 4 led1 section control 0: no 1: section control 3 led2 control 0: stpc control 1: off 2 led1 volume control 0: on mode1.5 is for led flash type control. mode1.4 is for led1 section control on/off. mode1.3 is for led2 section/stpc control. mode1.2 is for led1 volume control. 3. page register bit 7 6 5 4 3 2 1 0 page - - - pg4 pg3 pg2 pg1 pg0 the bits 0 ~ 4 in page register are used for page selection. once the page mode being defined (refe rring to the below section of ? option control function ? ), the working page is selected by the bits 0 ~ 4 in the page register. hence, the user can execute "ld page, value" instruction to change the working page of the voice entry group. not all of the bits 0 ~ 4 of page register are used in different page mode. they are listed as below table: page mode pg4 pg3 pg2 pg1 pg0 1 - page 8 - page ? ? ? 16 - page ? ? ? ? 32 - page ? ? ? ? ? where " " means don t care and " ? " means must be set prope rly. 4. en register bit 7 6 5 4 3 2 1 0 en0 x x tg2r tg1r x x tg2f tg1f en1 x x tg6r tg5r x x tg6f tg5f en0 or en1 is an 8 - bit register that stores the rising/falling edge enable or disable status information for all trigger pins, which determines whet her each trigger pin is retriggerable, non - retriggerable,
w523sxx (preliminary) - 6 - overwrite, or non - overwrite. the 8 - bit structure of this register and the rising or falling edge of the triggers corresponding to each bit are shown above. ? x ? indicates a ? don ? t care ? bit. the tg1, 2, 5, 6 represents triggers 1, 2, 5 and 6 respectively; the ? r ? represents the rising edge; and ? f ? represents the falling edge. when any one of the eight bits is set to ? 1 ? , the rising or falling edge of the corresponding trigger pin can be enabled, inte rrupting the current state. 5. stop register bit 7 6 5 4 3 2 1 0 stop x x x ste std stc stb sta the stop register stores stop output status information to determine the voltage level of each stop output pin. the 8 - bit structure of this register and the stop output pin corresponding to each bit are show as above table. the ? x ? indicates a ? don ? t care ? bit. when a particular stop bit is set to ? 1 ? , the corresponding stop signal will be an active high output. 6. r0 - r3 registers these four registers are 8 - b it register that stores the entry values of from 0 to 255 voice groups. r0 is a special register that can be incremented by "inc" instruction. option control function there are four types of option control in w523sxx. they can be determined by a declaratio n in the user s program file, but cannot be controlled by register. function mask option declaration definition defpage 1 256 interrupt vector/label for 1 page, 1 page in total (1 - page mode) defpage 8 256 interrupt vector/label f or 1 page, 8 pages in total (8 - page mode) defpage 16 128 interrupt vector/label for 1 page, 16 pages in total (16 - page mode) page mode configuration defpage 32 64 interrupt vector/label for 1 page, 32 pages in total (32 - page mode) normal normal mode operation operation mode cpu cpu mode operation osc_3mhz 3 mhz oscillator oscillator frequency osc_1.5mhz 1.5 mhz oscillator vout_dac dac (aud) output voice output type vout_pwm pwm output "defpage" determines the page operation mode in w523sxx. the default setting of the page mode is 1 - page mode. the 8 - page, 16 - page or 32 - page mode can be declared to extend the voice group entry from 256 to 2047 in powerspeech ? program. the w523sxx can communicate with an external microprocessor through the simple serial cpu interface, which is the same as the w583xx series. the cpu interface consists of the tg1, tg2, and stpa/busy pins. "normal" and "cpu" decide whether the operation mode of w523sxx will be normal mode or cpu mode. "osc_3mhz" and "osc_1.5mhz" select the frequency of th e system clock. "vout_dac" and "vout_pwm" select the voice output type.
w523sxx (preliminary) publication release date: oct 2000 - 7 - revision a5 interrupt vector allocation the w523sxx provides a total of 4 trigger inputs to communicate with the outside world. each trigger pin can invoke 2 dedicate interrupt vectors depending o n tg pins ? status (rising or falling). the table below shows the relationship between triggers ? status and interrupt vectors. interrupt vector trigger source 0 tg1f 1 tg2f 8 tg5f 9 tg6f interrupt vector trigger source 4 tg1r 5 tg2r 12 tg5r 13 tg6r 32 poi cpu interface the w523sxx can communicate with an external microprocessor through a simple serial cpu interface. the cpu interface consists of tg1, tg2 and stpa/busy pins, which are shown below: debounced ok. to clear the internal cpu counter for preventing the system from running away. (tg1f should be disabled.) t deb end t crd tg1 (data) tg2 (clock) stpa/busy aud/spk+ note: 1. t deb means the "debou nce time". 2. t crd is the "cpu reset delay" time. this should be more than 2.6 m s. 3. the "clock" frequency of the tg2 pin can be set in the range: 10 khz - 1 mhz. busy signal will output "high" after the end of transmission. the rising timing of busy signal is
w523sxx (preliminary) - 8 - dependent on the msb of data output on tg1 (data) pin. if msb is "1", busy will rise after the last rising edge of tg2 (clock) pin. if msb is "0", busy will rise after the rising edge that tg1 (data) returns to high. tg1 (data) tg2 (clk) busy 7 bits msb=0 40ns tg1 (data) tg2 (clk) busy 7 bits msb=1 40ns to place the w523sxx in cpu mode, program the code according to the following example. w523s15 cpu ; reserved word, used as a directive to notify the compiler for post processing. led1 freq2 poi: ld mode0,xx1xx0xxb ; bit2=0 busy ld en0, 0x00 h5+voice1+t5 end 34: ; direct trigger or cpu interrupt. h5+voice2+t5 end the defaulted operating mode in w523sxx is normal mode (or manual trigger mode), which is identified by the "normal" and "cpu" option control. to enter the cpu mode, the "cpu" declaration must be inserted in the declaration region of program (*.out). in cpu mode, the bit mode0.2, which is defined as stpa or busy selection for the stpa/busy pin, will be selected as "0" (busy output) automatically by the c ompiler unless otherwise specified explicitly by the stpa directive. the cpu, stpa, and busy directives can appear only in the first paragraph of the *.out files so that the compiler will automatically interpret them as stop definitions in the poi interrup t vector. if these directives are placed elsewhere, an error message will be issued during the compilation process. in the program example shown above, the external m c will transfer one byte data "34" to w523sxx. the number 34 (decimal) is equal to 0010001 0b (binary). the interface timing is shown below.
w523sxx (preliminary) publication release date: oct 2000 - 9 - revision a5 tg1 tg2 (data) (clock) 0 1 0 0 0 1 0 0 msb lsb <1> <2> <3> <4> deb t crd t <1> when tg1 is pulled low, the w523sxx stops playing voice or executing instruction and waits for data from the external m c. <2> if tg1 is debounced ok, the w523sxx will clear the cpu receiving buffer. <3> 8 - bit data are transferred by tg1 (data) and tg2 (clock). lsb is sent firstly. <4> tg1 returns to high and starts the cpu interrupt service. in this case w523s15 will play the h51+voice2+t51 sections and the stpa/busy pin is pulled h igh during the playing period. the tg1 pin, which is pulled high with a 500k w resistor, should be kept high during non - transmission periods to reduce power consumption. the external m c should be connected to the w523sxx by an inverted - type output port for better noise immunity. in cpu mode, the w523sxx stops operating upon the falling edge of the tg1 pin. for the cpu interface to work normally, tg1f should be disabled. thus, one suggestion is that tg1f, tg1r, tg2f, and tg2r should all be disabled in cpu mo de. the master frequency of the external m c, and hence the clock rate of tg1 and tg2, tends to vary among different vendors and applications. note: in cpu mode application, in case the last voice group entry point, 255, is no used, it should be typed ? end ? command to avoid abnormal operating. instruction set list there are two types of instruction in the w523sxx, unconditional and conditional instructions. the first types of instructions are executed immediately after they are issued. the second types of in structions are executed only when the conditions specified in the instruction are satisfied. all the instructions are listed in the following table. the cycle time for each instruction is 2/sampling frequency (fs). for example, fs = 6.0 khz, the cycle time is 333 m s. unconditional conditional jp g jp g @sts jp rn jp rn @sts ld en0, value ld en0, value @sts ld en1, value ld en1, value @sts ld modei, value ld modei, value @sts ld stop, value ld stop, value @sts ld page, value l d page, value @sts ld rn, value ld rn, value @sts end end @sts mv rn, rm mv rn, rm @sts inc inc @sts
w523sxx (preliminary) - 10 - legend: g: interrupt vector/label rn: r0 - r3 rm: r0 - r3 modei: mode0, mode1 value: 8 - bit data @sts can be the following: @last, @tgn_hi gh, @tgn_low, n = 1 - 4. absolute maximum rat ings parameter symbol conditions rated value unit power supply v dd - v ss - - 0.3 to +7.0 v input voltage v in all inputs v ss - 0.3 to v dd +0.3 v storage temp. t stg - - 55 to +150 c operating temp. t opr - 0 to +70 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. electrical character istics (t a = 25 c, v ss = 0v) dc characteristics parameter sym. conditions min. typ. max . unit dac output 2.4 3.0 5.5 v operating voltage v dd pwm output 2.4 3.0 5.5 v v il v ss ? 0.3 - 0.3 v dd v input voltage v ih 0.7 v dd - v dd i sb1 v dd = 3v, all i/o pins unconnected, no playing 1 m a standby current i sb2 v dd = 5v, all i/o pin s unconnected, no playing 1 m a i op1 v dd = 3v, no load 500 m a operating current (ring type) i op2 v dd = 5v, no load 1 ma input current of tg1 - tg4 pins i in1 v dd = 3v, vin = 0v - 8 m a input current of test pin i in2 v dd = 3v, vin = 3v 30 m a inpu t current of sel, reset i in3 v dd = 3v, vin = 0v - 8 m a spk (d/a full scale) i dac v dd = 4.5v, rl = 100 w - 4.0 - 5.0 - 6.0 ma
w523sxx (preliminary) publication release date: oct 2000 - 11 - revision a5 i ol1 v dd = 3v, vout = 0.4v 0.8 ma output current of stpa - stpe i oh1 v dd = 3v, vout = 2.7v - 0.8 ma i ol2 100 ma output curre nt of spk+, spk - i oh2 v dd = 3v, rl = 8 w - 100 ma ac characteristics parameter sym. conditions min. typ. max. unit ring oscillator, rosc = 270 k w 2.7 3 3.3 mhz oscillation frequency ( w58300 ice chip) fosc1 ring oscillator, rosc = 560 k w 1.3 1.5 1.7 mhz ring oscillator, rosc = 1.2 m w 2.7 3 3.3 mhz oscillation frequency ( w523sxx production chip) fosc2 ring oscillator, rosc = 2.4 m w 1.3 1.5 1.7 mhz oscillation frequency deviation by voltage drop d fosc2 fosc2 f(3v) - f(2.4v) f(3v) 7.5 % instruction cycle time tins fosc = 3 mhz, sr = 6 khz 1/3 ms poi delay time t pd fosc = 3 mhz 160 ms long debounce time t debl 50 ms short debounce time t debs fosc = 3 mhz, sr = 6 khz 400 m s bonding pad diagram 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
w523sxx (preliminary) - 12 - pad no. pad name pad no. pad name 1 v dd1 12 led2/stpc 2 reset 13 stpd 3 test 14 stpe 4 tg1 15 vss2 5 tg2 16 vdd2 6 tg5 17 spk - 7 tg6 18 a ud/spk+ 8 vss1 19 osc 9 led1 10 stpa/busy 11 stpb typical application circuit 1. dac output: note: 1. in principle, the playing speed determined by rosc should correspond to the sampling rate during the coding phase. the playing speed may be adjusted by varing rosc, however. vdd (1.8v ~ 5.5v) tg1 tg2 tg5 tg6 /reset vdd2 vdd1 test led1 osc stpa/busy stpb vss2 vss1 led2/stpc stpd stpe aud/spk+ spk - rosc rs cs npn t ? x speaker 8 ohm ? watt led 100 ohm led 100 ohm w52 3sxx
w523sxx (preliminary) publication release date: oct 2000 - 13 - revision a5 2. rs is an optional current - dividing resistor. if rs is added, the resistance should be between 390 and 820 ohm. 3. the typical ro sc = 1.2 mohm for 3 mhz fosc; and rosc = 2.4 mohm for 1.5 mhz fosc. 4. cs is optional. 5. the dc current gain of the npn transistor ranges from 120 to 200. 6. all unused trigger pins can be left open because of their internal pull - high resistance. 7. the osc layout in customer ? s pcb should be as closed as the osc pad to avoid noise coupling. 8. the chip ? s substrate must be wired to vss. 2. pwm output: note: 1. in principle, the playing speed determined by rosc should correspond to the sampling rate during the c oding phase. the playing speed may be adjusted by varing rosc, however. 2. the typical rosc = 1.2 mohm for 3 mhz fosc; and rosc = 2.4 mohm for 1.5 mhz fosc. 3. the capacity, 10 uf, is necessary to reduce voltage fluctuation while pwm outputting. 4. all unused trigg er pins can be left open because of their internal pull - high resistance. 5. the osc layout in customer ? s pcb should be as closed as the osc pad to avoid noise coupling. 6. the chip ? s substrate must be wired to vss. vdd (2.4v ~ 5.5v) tg1 tg2 tg5 tg6 /reset vdd2 vdd1 test led1 osc stpa/busy stpb vss2 vss1 led2/stpc stpd stpe aud/spk+ spk - rosc speaker 8 ohm ? watt led 100 ohm led 100 ohm w523sxx 10 uf
w523sxx (preliminary) - 14 - revision history in w523sxx data shee t version date editor description a1 may - 1 - 2000 steven lin initial issued a2 may - 19 - 2000 steven lin 1. add dac and pwm application circuits. 2. add pwm voltage as 2.4v ~ 5.5v in dc characteristic table. a3 jul - 3 - 2000 steven lin 1. general description, 3 rd line : ? ? and inc commands and ten programmable registers provide ? ? 2. feature, 1st line: 1.8 - 5.5 volts for dac output and 2.4 ? 5.5 volts for pwm output. 3. feature, 4 th line: ? new high fidelity synthesis algorithm ? it ? s deleted for redundant. 4. feature, last line: ? up to 256 voice groups can be used in single page mode; or extended to 2,048 voice groups in multi page mode, such as 8 - page, 16 - page and 32 - page. ? 5. function description: modified the description for more easy readable. 6. stop register: when a particular sto p bit is set to ? 1 ? , the corresponding stop signal will be an active high output. 7. add cpu interface description in timing diagram, operation and notified. 8. application circuit: add a note in number 7, ? the osc layout on customer ? s pcb should be as closed as the osc pad to avoid noise coupling. ? for both of dac and pwm output application circuit. a4 jul - 25 - 2000 steven lin 1. application circuit in pwm output diagram: add a capacity, 10 uf, between vdd and gnd to reduce voltage fluctuation while pwm outputting. a5 oct - 25 - 2000 steven lin 1. feature, 1 st line: operating voltage 2.4 ~ 5.5 volts for both dac and pwm output. 2. dc spec., dac voltage: minimum 2.4v. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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